1. Field of the Invention
The present invention relates to the alleviation of charge buildup on integrated circuit components during dry plasma etching of semiconductor interconnect feedthrough structures.
2. Brief Description of the Background Art
In the quest for ever-higher circuit densities in modem very large scale integrated circuit semiconductors, engineers have moved from conventional chip layouts, in which interconnects between active regions on the chip are formed by metallic, generally aluminum, conductors in the plane of the devices, connected layer-to-layer mostly at the outer edges, to dual damascene architecture. In a dual-damascene structure, multiple layers of active devices are separated by layers of dielectric material, which are traversed within a given layer by trenches filled with conductive materials, which in turn are connected layer-to-layer by interconnects formed by filling through-openings with conductive materials. These contact openings, typically referred to as vias, are etched through the intervening dielectric layer or layers.
These trenches and contact openings are etched in the dielectric layers by means of dry etching, utilizing a plasma generated by exposing appropriate etchant source gases, often halogen-comprising gases, to powerful electromagnetic fields. The resultant plasma consists of free electrons, positively charged ions, and various high energy species of the plasma source gas. The workpiece to be etched typically has a desired pattern superimposed upon it in some form of mask. The mask is generally formed photolithographically upon an organic photoresist material, which is developed to provide open areas where etching is desired.
To achieve anisotropic etching, that is, etching which is generally unidirectional, so that positively charged active species travel vertically downward through the opening in the resist layer toward the etch front within the deepening etched feature, the workpiece is maintained at a negative electrical potential. This serves to accelerate positively-charged species toward the target surface, but leaves the electrons in the plasma less able to penetrate to the bottom of the etched feature.
This phenomenon, the ability of only positively charged high energy species to penetrate to the lower regions of the etch front, while electrons accumulate near the top of the opening, is called electron shading. The electron shading effect is self-perpetuating, since the accumulation of electrons near the opening creates a local electric field which further repels electrons from entering, but continues to easily permit the positively charged high energy species, such as ions, accelerated by the electrical potential, to penetrate to the full depth of the etched feature. When the resultant positive charge near the bottom of the feature becomes sufficiently high, it results in a tunneling current which can do severe damage to underlying layers.
The aspect ratio of a feature typically refers to the ratio of the depth of the feature to its smallest horizontal cross-sectional dimension. The electron shading effect, and the resultant charging damage to the structure, begin to be significant in etched features having an aspect ratio greater than about 2. The electron shading effect gets worse as the aspect ratio increases, since the electron accumulation near the opening and top sidewalls of the feature makes it increasingly difficult for anything but the positively charged high energy species to get past that entrance and any distance down into the deepening etched feature.
FIGS. 1A-1G show a typical set of process steps for creating a dual damascene structure. Electron shading effects are often a serious problem during fabrication of dual damascene structures.
In FIG. 1A, a conductor 102, such as copper or aluminum or alloys thereof, is embedded in a dielectric 100. An upper portion of the conductor is contacted at sidewall 103 by a layer of a first dielectric hardmask 104. The upper surface 105 of dielectric hardmask layer 104 and the upper surface 107 of conductor 102, are covered by an etch stop layer 106, which is typically a dielectric such as Si3N4, SiON, or SiC. A layer of dielectric 108, which is typically a low-k dielectric overlies the etch stop layer 106, and is itself overlain by a second dielectric hardmask layer 110. (A xe2x80x9clow-k dielectricxe2x80x9d is one with a relative dielectric permitivity, xcexa, less than that of SiO2, or less than about 3.9.) A via or other contact opening 116 has been etched through dielectric hardmask layer 110 and dielectric layer 108, to the etch stop layer 106.
In FIG. 1B, a layer of photoresist material 118 has been applied covering the surface of the structure, and partially filling in the contact opening 116.
In FIG. 1C, the photoresist layer 118 has been developed, providing a patterned mask for etching of a trench which will overlie the contact opening 116.
In FIG. 1D, anisotropic etching is being performed to form trench 120 through dielectric hardmask layer 110 and partly into dielectric layer 108. It is at this point in the prior art etching process to produce trench 120 that the problem of electron shading arises, as illustrated in FIG. 1D. Accumulations of excess electrons 130 form an unbalanced negative charge near the entrance 126 and on the upper sidewalls 128 of contact opening 116, and to a lesser extent on the upper sidewalls 124 of developing trench 120. As positively charged energetic species 132 continue to reach the bottom 117 of contact opening 116, but few if any electrons 130 are able to do so, a corresponding accumulation of excess positive charge builds up there, causing a tunneling current 134 which can do serious damage to the underlying conductor 102. Such damage is illustrated by numerals 136 in FIGS. 1E through 1G.
In FIG. 1E, trench 120 has been etched, directly over contact opening 116, through dielectric hardmask layer 110 and dielectric layer 108. At the same time, the bottom 117 of contact opening 116 has been etched down at least partially through etch stop layer 106.
Subsequently, the residue of photoresist layer 118 has been removed, as illustrated in FIG. 1F. Finally, in FIG. 1G, the remainder of the etch-stop layer 106 at the bottom of contact opening 116 has been removed, to permit electrical contact with the conductor 102, as illustrated in FIG. 1G. Contact opening 116 and trench 120 are subsequently filled with conductive material to form the interconnect between the lower and upper layers of devices. This process can be repeated as desired to form a multilayered structure in which the active layers are electrically interconnected by conductive fill material placed in the contact openings and trenches.
Various techniques have been used in an attempt to reduce or eliminate charging damage to semiconductor devices occurring during the etching process. For example, U.S. Pat. No. 5,468,341, to Samukawa (See Abstract.), discloses a method and apparatus wherein pulse modulation of the electric fields producing the etching plasma are controlled to produce a pulse interval shorter than about 10 xcexcsec. This is said to provide advantageous process conditions, including a reduction in charge accumulation. U.S. Pat. No. 5,441,849, to Shiraishi, et al (See abstract.) discloses a method of solving a distinct but similar problem of electrical charge accumulation During the formation of the latent image in a photoresist layer, the photoresist is exposed to a charged particle beam, where electrical charge accumulation causes positional deviation of the imaged pattern. By using a bottom-resist layer of material which can be rendered conductive by simultaneous exposure to actinic radiation (such as ultraviolet light, X-ray, or infrared light), the charge accumulation is alleviated.
The present invention reduces the amount of charging damage caused by electron shading during the process of plasma etching a trench overlying an existing electrical contact opening. This is accomplished by introducing a processing step that adds a protective layer of conductive material, generally a metal, conductive metal nitride, conductive metal oxide, or a combination thereof, lining the contact opening. This layer provides a conductive path for maintaining charge balance in the etched structures during the etching process. This protective conductive layer greatly reduces or eliminates the charge buildup caused by electron shading, and the damage done to the layers at or near the bottom of the contact opening by the tunneling current induced by such charge buildup, during trench etching. To the extent that the protective conductive layer also remains present between the dielectric layer being etched and a photoresist layer defining the trench, that protective conductive layer acts to equalize charge laterally at the top of the dielectric layer.
For purposes of describing an embodiment of the invention, FIGS. 2A through 2I illustrate a method of reducing plasma-induced charging damage during etching of a trench in a dielectric layer which forms part of a dual damascene semiconductor structure. For example, the method comprises:
a. providing a semiconductor structure including an electrical contact opening through a dielectric layer overlying an etch stop layer, which etch stop layer overlies a conductive region in the semiconductor structure;
b. applying a protective layer of a conductive material over surfaces of the electrical contact opening and over exposed horizontal surfaces adjacent the contact opening;
c. applying a layer of photoresist material over the upper surface of the semiconductor structure;
d. patterning the layer of photoresist material; and
e. etching a trench overlying the electrical contact opening and through a portion of the dielectric layer, wherein charging damage to the semiconductor structure which occurs during etching is reduced by the presence of the layer of protective conductive material.
Subsequent processing steps are carried out to remove photoresist residue and an etch stop at the bottom of the contact opening. The resultant dual damascene structure exhibits a contact opening having sidewalls lined with the protective conductive layer material, ready for filling of the trench and contact opening with a conductive material. Additional steps may then be carried out to add additional layer or layers of materials to provide a particular semiconductor device.
When the protective conductive layer comprises a material which can also serve as a diffusion barrier layer for the conductive fill material used to fill the trench and contact opening, additional processing steps to add such a barrier layer may be avoided.
In instances where the conductive protective layer can function as an anti-reflective coating (xe2x80x9cARCxe2x80x9d) during fabrication of the trench overlying the contact opening, separate application of an ARC layer may be avoided.